1. Field of the Invention
This invention relates to a direct digital frequency synthesizer (DDFS) and more specifically to a hardware-efficient phase-to-amplitude mapping design.
2. Description of the Related Art
Direct digital frequency synthesizers (DDFS) are becoming an alternative to analog-based PLL synthesizers in systems exemplified by chirp radar, frequency agile radio, agile clock synthesis, phase array antennas and automatic test equipment because of sub-Hertz resolution and fast frequency switching properties. To exploit DDFS in broadband communication systems, DDFS designs operating at GHz-range clock frequencies are required. However, most DDFS designs are working up to a few hundred MHz-range frequencies. B. D. Yang et al recently published results for a single-chip DDFS design with an integrated DAC working at 800 MHz clock frequency (fCLK) having 55 dBc spurious-free dynamic range (SFDR) at low synthesized output frequencies (fOUT) (IEEE J. Solid State Circuits, vol. 39, no. 5, pp. 761-774, 2004). Note however that SFDR drops to below 25 dBc at fOUT CLose to 400 MHz, which is not suitable for high-spectral purity communication systems.
As shown in FIG. 1, the basic principle of a DDFS 10 involves the use of a phase accumulator 12 to calculate phase angles around the unit cirCLe. Phase accumulator 12 provides a certain frequency tuning resolution when clocked at a given frequency, desirably sub-Hertz resolution at GHz frequencies. The M-bit phase angle 14 is truncated to N bits and passed to a phase-to-amplitude mapping circuit 16, which together with the phase accumulator make up the numerically controlled oscillator (NCO), to generate the corresponding R-bit sinusoid amplitude samples 18. These samples are passed to a digital-to-analog converter (DAC) 20 then filtered by a low-pass filter to generate the synthesized analog signal 22. Input control circuit 24 controls the output frequency and/or phase by providing P-bit frequency control words (FCW) or phase control words (PCW) to the phase accumulator depending on a ‘Mode’ to change output frequency or modulate phase. The phase accumulator integrates the control word every clock cycle and overflows through zero periodically resulting in a repeating ramp output.
Many architectures and design attempts have been reported in literature for the phase-to-amplitude mapping circuit 16 in DDFS. ROM-based mappings include uncompressed, Sunderland architecture and Nicholas architecture. Computation mappings include CORDIC and other angular rotation algorithms and parabolic, polynomial and linear approximation. This circuit is the most challenging unit among the digital parts of DDFS, because it usually limits operating speed, requires a large area, and consumes more power than any other circuits.
Linear approximation is one of the simplest computational ways to convert phase data to sine amplitude. As shown in FIGS. 2a and 2b, one quarter period 30 of sine wave 32 is divided into a number of segments 34 (N) and within those segments the sine amplitude 36 is computed with a linear function, Y=aX +b. Each linear function has a starting value of bk and an ending point at b(k+1) with a slope coefficient ‘ak’, 0<k<N. N is dictated by the design goals, such as SFDR. A certain number of the MSBs of the R-bit mapping input are used to decode the segment number giving bk and b(k+1) and the remaining LSBs are used to compute an intermediate point akX on the linear segment between bk and b(k+1).
U.S. Pat. No. 6,657,573 to Langlois et al. describes an implementation of a phase-to-sinusoid amplitude conversion system using linear approximation in which each linear segment is defined with a lower horizontal-axis bound; a lower vertical-axis bound; and a slope represented as a sum of a plurality of slope elements. Based on the approximation and for a given phase angle a set of values are evaluated, for each linear line segment, representing a product of (i) a horizontal displacement representing a difference between the prescribed phase angle and the lower horizontal-axis bound xi of a selected linear line segment where, for example, xi<X<xi+1 and (ii) each one of the slope elements of the selected linear line segment. The approximation of the sinusoidal amplitude is then obtained by adding one of the sets of values determined above with the lower vertical-axis bound of the selected linear line segment.
As shown in Langlois' FIG. 4, the addend generator/selector module receives two signals: the control signal that is log2(S) bits wide and the data signal that is W-log2(S) bits wide where S is the number of linear segments. The control signal is used to select appropriate input ports from (P+1) multiplexers each having S input ports where P represents the number of powers of two that are summed to equate one slope coefficient. The input ports of the first P multiplexers are provided with output from shift/sign inversion (SI) block mechanisms. Each SI block includes a shifter block and a +/−1 multiplier. The number of the shift position imposed on the data signal depends on the portion of a slope mi that is calculated by the shifter block (i.e., the block is responsible for the multiplication by a single power of two, which is performed in binary by a simple shift). The +/−1 multiplier inverts the sign of the shifted data, if necessary, as defined by the relevant segment slope. The input ports of the multiplexer (P+1) are provided with constant values provided by a plurality of constant data (CD) blocks, each providing a digital word that represents a segment's lower vertical axis limit yi, which are selected to maximize the output spectral purity of the DDFS. The outputs from the multiplexers are processed by the adder module.
Although an advancement over traditional architectures that rely on look-up tables and multipliers, Langlois' addend generator/selector module uses multiple multiplexers that are S bits wide. Langlois hardwires the shifting of the data signal to the inputs of each multiplexer and then uses the control signal to select the input that corresponds to the segment number. Typical, converters divide quadrants into S=32 segments or larger, which means this approach would require multiple 32-bit or wider multiplexers. These wideband multiplexers use considerable hardware resources, thus requiring considerable area and consuming significant amounts of power.